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SDRAM
Austin Semiconductor, Inc. 512K x 32 x 4 Banks (64-Mb)
Synchronous SDRAM
FEATURES
* Full Military temp (-55C to 125C) processing available * Configuration: 512K x 32 x 4 banks * Fully synchronous; all signals registered on positive edge of system clock * Internal pipelined operation; column address can be changed every clock cycle * Internal banks for hiding row access/precharge * Programmable burst lengths: 1, 2, 4, 8 or full page * Auto Precharge, includes CONCURRENT AUTO PRECHARGE and Auto Refresh Modes * Self Refresh Mode (IT & ET) * 64ms, 4,096 cycle refresh (IT & ET) * <16ms 4,096 cycle refresh (XT) * WRITE Recovery (tWR = "2 CLK") * LVTTL-compatible inputs and outputs * Single +3.3V 0.3V power supply
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 WE CAS RAS CS NC BA0 BA1 A10 A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
AS4SD2M32
PIN ASSIGNMENT (Top View)
86-Pin TSOPII
86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS
OPTIONS
* Plastic TSOPII-EX
*
MARKING
DGX -6 -7 -7.5 IT ET XT***
VSSQ DQ21 DQ22 VDDQ DQ23 VDD
Timing (Cycle Time) 6.0ns CL=3 7.0ns CL=3 7.5ns CL=3 Operating Temperature Ranges -Industrial Temp (-40C to 85 C) -Enhanced Temp (-45C to +105C) -Extended Temp (-55C to 125C)
*
2M x 32 Configuration 512K x 32 x 4 Refresh Count 4K Row Addressing 4K (A0-A10) Bank Addressing 4 (BA0, BA1) Column Addressing 256 (A0-A7)
KEY TIMING PARAMETERS
SPEED CLOCK ACCESS TIME GRADE FREQUENCY CL = 2** CL = 3**
**CL = CAS (READ) latency ***Consult Factory
SETUP TIME 1.5ns
HOLD TIME 0.8ns
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AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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SDRAM
Austin Semiconductor, Inc.
GENERAL DESCRIPTION
The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A10 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random operation. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, randomaccess operation. The 64Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a powersaving, power-down mode. All inputs and outputs are LVTTLcompatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access.
AS4SD2M32
FUNCTIONAL BLOCK DIAGRAM
CLK CKE CS RAS CAS WE
DQM0-3 COMMAND DECODER & CLOCK GENERATOR
DATA IN BUFFER
32 32
MODE REGISTER
11
REFRESH CONTROLLER
DQ 0-31
SELF REFRESH CONTROLLER
A10
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1
11
DATA OUT BUFFER
32 32
VDD/VDDQ GND/GNDQ
REFRESH COUNTER
2048 2048 2048 2048
ROW DECODER
MULTIPLEXER
MEMORY CELL ARRAY
11
ROW ADDRESS LATCH
11
ROW ADDRESS BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN ADDRESS LATCH
256 (x 32)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN DECODER
COLUMN ADDRESS BUFFER
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SDRAM
Austin Semiconductor, Inc. PIN DESCRIPTIONS
PIN NUMBER 68 SYMBOL CLK TYPE DESCRIPTION Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also Input increments the internal burst counter and controls the output registers. Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SLEF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is Input synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Chip Select: CS\ enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS\ is registered HIGH. CS\ provides for external bank selection on systems with multiple banks. CS\ in considered part of the command code. Command Inputs: WE\, CAS\ and RAS\ (along with CS\) define the command being entered. Input/Output Mask: DQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DWM is sampled HIGH during a WRITE cycle. The outptu buffers are placed in a High-Z state (two-clock latency) when DQM is sampled HIGH during a READ cycle. DQM0 corresponds to DQ0-7, DQM2 to DQ16-23, DQM3 to DQ24-31 Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
AS4SD2M32
67
CKE
20
CS\
Input
17, 18, 19
WE\, CAS\, RAS\
Input
16,71,28,59
DQM0, DQM1, DQM2, DQM3
Input
22, 23
BA0, BA1
Input
25, 26, 27, 60, 61, 62, 63, 64, 65, 66, 24
A0 - A10
Address Inputs: A0-A12 are sampled during the ACTIVE command (row address A0-A12) and READ/WRITE command (column-address A0-A8; with A10 defining auto precharge) to select one location out of the memory array in the respective Input bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be prechaged (A10 [HIGH]) or bank selected by (A10 [LOW]). The address inputs also provide the op-code during LOAD MODE REGISTER COMMAND.
2,4,5,7,8,10,11,13,74,76,77, 79,80,82,83,85,31,33,34,36,3 7,39,40,42,45,47,48,50,51,53 ,54,56 14, 21, 30, 57, 69, 70, 73 3,9,35,41,49,55,75,81 6,12,32,38,46,52,78,84 1,15,29,43 44,58,72,86
AS4SD2M32 Rev. 1.0 1/08
DQ0 - DQ31
I/O
Data Input/Output: Data bus
NC VDDQ VSSQ VDD VSS
No Connect: These pins should be left unconnected. DQ Power: Isolated DQ power to the die for improved noise Supply immunity. DQ Ground: Isolated DQ ground to the die for imporved noise Supply immunity. Supply Power Supply: +3.3V 0.3V Supply Ground
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SDRAM
Austin Semiconductor, Inc.
FUNCTIONAL DESCRIPTION
In general, the 64Mb SDRAMs are quad-bank DRAMs that operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0 - A10 select the row). The address bits (A0 - A7) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 1. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0 - M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4 - M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10, M11 and M12 are reserved for future use. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential types. The fullpage burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The clock is uniquely selected by A1-A8 when the burst length is set to two; by A2-A7 when the burst length is set to four, and by A3-A7 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, shown in table 1.
AS4SD2M32
Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100s delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100s period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100s delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be preformed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command.
Register Definition
MODE REGISTER The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the
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SDRAM
Austin Semiconductor, Inc.
AS4SD2M32
FIGURE 1: Mode Register Definition TABLE 1: Burst Definition
BURST LENGTH
BA1 BA0
2
4
8
Full Page (y)
STARTING ORDER OF ACCESSES WITHIN A BURST COLUMN TYPE = SEQUENTIAL TYPE = INTERLEAVED A0 0 0-1 0-1 1 1-0 1-0 A1 A0 00 0-1-2-3 0-1-2-3 01 1-2-3-0 1-0-3-2 10 2-3-0-1 2-3-0-1 11 3-0-1-2 3-2-1-0 A2 A1 A0 000 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 001 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 010 2-3-4-5-6-7-0-12-3-0-1-6-7-4-5 011 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 100 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 101 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 110 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 111 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Cn, Cn+1, Cn+2, Cn+3, n=A0-A7 Cn+4... Not Supported (location 0-y) ...Cn-1, Cn...
NOTES:
1. For full-page access: y=512 2. For a burst length of two, A1-A7 select the block-of-two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2-A7 select the block-of-four burst; A0-A1 selects the starting column within the block. 4. For a burst length of eight, A3-A7 select the block-of-eight burst; A0-A2 selects the starting column within the block. 5. For a full-page burst, the full row is selected and A0-A7 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-A7 select the unique column to be accessed, and mode register bit M3 is ignored.
AS4SD2M32 Rev. 1.0 1/08
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SDRAM
Austin Semiconductor, Inc.
CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Table 2 below indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
AS4SD2M32
Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes are reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9=0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9=1, the programmed burst length applies to READ bursts, but write accesses are single-location (non-burst) accesses.
FIGURE 2: CAS Latency
TABLE 2: CAS Latency
SPEED -6 -7 -75 ALLOWABLE OPERATING FREQUENCY (MHz) CAS CAS LATENCY = 2 LATENCY = 3 100 166 100 143 100 133
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SDRAM
Austin Semiconductor, Inc.
COMMANDS
Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following the Operation section; these tables provide current state/next state information. COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS\ is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The mode register is loaded via inputs A0-A9, BA0, BA1 . See mode register heading in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met.
AS4SD2M32
ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A10 selects the row. The row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A8 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs
TRUTH TABLE 1: COMMANDS AND DQM OPERATION1
FUNCTION COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z CS\ RAS\ CAS\ WE\ H X X X L H H H L L H H L H L H L L L L L H H L L L L H H L L L L L H L DQM ADDR DQs NOTES X X X X X X X Bank/Row X 3 8 Bank/Col X 4 L/H L/H X X X X L H
8
Bank/Col Valid X Active Code X X X
4 5 6, 7 2 8 8
Op-Code X Active High-Z
NOTE:
1. CKE is HIGH for all commands shown except SELF REFRESH. 2. A0-A9, BA0, BA1 define the op-code written to the mode register, and A12 should be driven LOW. 3. A0-A10 provide row address, and BA0, BA1 determine which bank is made active. 4. A0-A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. 5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are "Don't Care." 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. 8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
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SDRAM
Austin Semiconductor, Inc.
WRITE (continued) selects the bank, and the address provided on inputs A0-A8 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, an in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. AUTO PRECHARGE Auto precharge is a feature which performs the same individual-bank PRECHARGE functions described above, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A PRECHARGE of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where AUTO PRECHARGE does not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Operation section of this data sheet. BURSTTERMINATE The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently
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AS4SD2M32
registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet. AUTO REFRESH (IT & ET Temp options ONLY) AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS\-BEFORE-RAS\ (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be precharged prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP has been met after the PRECHARGE command as shown in the Operations section. The addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. The 64Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (tREF), regardless of width operation. Providing a distributed AUTO REFRESH command every 7.81s will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms. SELF REFRESH (IT & ET Temp options ONLY) The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like and AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become "Don't Care" with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR because time is required for the completion of any internal refresh in progress. Upon exiting the self refresh mode, an AUTO REFRESH commands should be immediately be performed for all addresses. The SELF REFRESH and AUTO REFRESH option are available with the IT and ET temperature options. They are not available with the XT temperature options.
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SDRAM
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OPERATION
BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Figure 3). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in Figure 4, which covers any case where 2 < tRCD (MIN)/ tCK < 3. (The same procedure is used to convert other specification limits from time units to clock cycles.) A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.
AS4SD2M32
FIGURE 3: Activating a Specific Row in a Specific Bank
A10
FIGURE 4: Example - Meeting tRCD (MIN) When 2 < tRCD (MIN)/ tCK < 3
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SDRAM
Austin Semiconductor, Inc.
READs READ bursts are initiated with a READ command, as shown in Figure 5. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 6 shows general timing for each possible CAS latency setting. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to the start address and continue.)
AS4SD2M32
Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a complete burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 7 for CAS latencies of two and three; data element n+3 is either the last of a burst of four or the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Figure 8, or each subsequent READ may be performed to different bank.
FIGURE 5: READ Command
CLK
FIGURE 6: CAS Latency
CKE
CS\
RAS\
CAS\
WE\
A0-A7
A8, A9
A10
BA0, 1
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SDRAM
Austin Semiconductor, Inc.
FIGURE 7: Consecutive READ Bursts
AS4SD2M32
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SDRAM
Austin Semiconductor, Inc.
FIGURE 8: Random READ Accesses
AS4SD2M32
AS4SD2M32 Rev. 1.0 1/08
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SDRAM
Austin Semiconductor, Inc.
Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be immediately followed by data from a WRITE command (subject to bus turn-around limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. The DQM input is used to avoid I/O contention, as shown in Figures 9 and 10. The DQM signal must be asserted (HIGH) at least two clocks prior to the write command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z), regardless of the state of the DQM signal; provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 10, the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 10 shows the case where the additional NOP is needed. A fixed-length READ burst may be followed by, or trun-
AS4SD2M32
cated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 11 for each possible CAS latency; data element n+3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 12 for each possible CAS latency; data element n+3 is the last desired data element of a longer burst.
FIGURE 9: READ to WRITE
FIGURE 10: READ to WRITE With Extra Clock Cycle
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SDRAM
Austin Semiconductor, Inc.
AS4SD2M32
FIGURE 11: READ to PRECHARGE
AS4SD2M32 Rev. 1.0 1/08
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SDRAM
Austin Semiconductor, Inc.
AS4SD2M32
FIGURE 12: Terminating a READ Burst
AS4SD2M32 Rev. 1.0 1/08
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SDRAM
Austin Semiconductor, Inc.
WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 13. The starting column and blank addresses are provided with the WRITE command, an auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixedlength burst, assuming no other commands have been initiated, the DQs will be ignored (see Figure 14). A full-page burst will continue until terminated. (At the end of the page, it will wrap to the start address and continue.)
AS4SD2M32
Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 15. Data n+1 is either the last of a burst of two or the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 16, or each subsequent WRITE may be preformed to a different bank.
FIGURE 14: WRITE Burst FIGURE 13: WRITE Command
CLK
CKE
CS\
RAS\
CAS\
WE\
FIGURE 15: WRITE to WRITE
A0-A9 A10
BA0, 1
AS4SD2M32 Rev. 1.0 1/08
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SDRAM
Austin Semiconductor, Inc.
Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be immediately followed by a READ command. Once the READ command is registered, the data inputs will be ignored, and WRITEs will not be executed. An example is shown in Figure 17. Data n+1 is either the last of a burst of two or the last desired of a longer burst. Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a fullpage WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is registered. The auto precharge mode requires a tWR of at least one clock plus time, regardless of frequency. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the
AS4SD2M32
clock edge coincident with, the PRECHARGE command. An example is shown in Figure 18. Data n+1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. The precharge can be issued coincident with the first coincident clock edge (T2 in Figure 18) on an A1 Version and with the second clock on an A2 Version (Figure 18). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that is requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
FIGURE 16: Random WRITE Cycles FIGURE 18: WRITE to PRECHARGE
FIGURE 17: WRITE to READ
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SDRAM
Austin Semiconductor, Inc.
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncate a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 19, where data n is the last desired data element of a longer burst. PRECHARGE The PRECHARGE command (see Figure 20) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care". Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.
AS4SD2M32
POWER-DOWN Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power saving while in standby. The device may not remain in the power-down state longer then the refresh period (64ms) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS). See Figure 21.
FIGURE 20: PRECHARGE Command
FIGURE 19: Terminating a WRITE Burst
A0-A9
FIGURE 21: Power-Down
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SDRAM
Austin Semiconductor, Inc.
CLOCK SUSPEND The clock suspend mode occurs when a column access/ burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, "freezing" the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspected internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See examples in Figure 22 and 23).
AS4SD2M32
Clock suspend more is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0).
FIGURE 22: Clock Suspend During WRITE Burst
FIGURE 23: Clock Suspend During READ Burst
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SDRAM
Austin Semiconductor, Inc.
CONCURRENT AUTO PRECHARGE An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. ASI SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below.
AS4SD2M32
READ with Auto Precharge 1. Interrupted by a READ (with or without auto precharge); A READ to bank m will interrupt a READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 24). 2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).
FIGURE 24: READ With Auto Precharge Interrupted by a READ
FIGURE 25: READ With Auto Precharge Interrupted by a WRITE
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SDRAM
Austin Semiconductor, Inc.
WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge); A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 26).
AS4SD2M32
4. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Figure 26).
FIGURE 26: WRITE With Auto Precharge Interrupted by a READ
FIGURE 27: WRITE With Auto Precharge Interrupted by a WRITE
AS4SD2M32 Rev. 1.0 1/08
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SDRAM
Austin Semiconductor, Inc.
TRUTH TABLE 2: CKE1,2,3,4
CKEn-1 CKEn L L CURRENT STATE Power-Down Self Refresh Clock Suspend Power-Down Self Refresh Clock Suspend All Banks Idle All Banks Idle Reading or Writing COMMANDn X X X COMMAND INHIBIT or NOP COMMAND INHIBIT or NOP X COMMAND INHIBIT or NOP AUTO REFRESH VALID See Truth Table 3 ACTIONn Maintain Power-Down Maintain Self Refresh Maintain Clock Suspend Exit Power-Down Exit Self Refresh Exit Clock Suspend Power-Down Entry Self Refresh Entry Clock Suspend Entry NOTES
AS4SD2M32
L
H
5 6 7
H H
L H
NOTES:
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n+1 (provided that tCKS is met). 6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during tXSR period. 7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n+1.
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SDRAM
Austin Semiconductor, Inc.
AS4SD2M32
NOTES
TRUTH TABLE 3: CURRENT STATE BANK n, COMMAND TO BANK n1,2,3,4,5,6
CURRENT STATE CS\ RAS\ CAS\ WE\ COMMAND (ACTION) H X X X COMMAND INHIBIT (NOP/Continue previous operation) ANY L H H H NO OPERATION (NOP/Continue previous operation) L L H H ACTIVE (Select and active row) L L L H AUTO REFRESH Idle L L L L LOAD MODE REGISTER L L H L PRECHARGE L H L H READ (Select column and start READ burst) Row Active L H L L WRITE (Select column and start WRITE burst) L L H L PRECHARGE (Deactivate row in bank or banks) L H L H READ (Select column and start new READ burst) Read L H L L WRITE (Select column and start WRITE burst) (Auto Precharge L L H L PRECHARGE (Truncate READ burst, start PRECHARGE) Disabled) L H H L BURST TERMINATE L H L H READ (Select column and start READ burst) Write L H L L WRITE (Select column and start new WRITE burst) (Auto Precharge L L H L PRECHARGE (Truncate WRITE burst, start PRECHARGE) Disabled) L H H L BURST TERMINATE
7 7 11 10 10 8 10 10 8 9 10 10 8 9
NOTES:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth Table 4. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the row active state. Read w/ Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/ Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
(continued on next page)
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SDRAM
Austin Semiconductor, Inc.
NOTES (continued):
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the SDRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the SDRAM will be in the all banks idle state. Precharging All: States with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all banks are to be precharged, all must be in valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank. 10. READs or WRITEs listed in the Command column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 11. Does not affect the state of the bank and acts as a NOP to that bank.
AS4SD2M32
AS4SD2M32 Rev. 1.0 1/08
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SDRAM
Austin Semiconductor, Inc.
AS4SD2M32
NOTES
TRUTH TABLE 4: CURRENT STATE BANK n, COMMAND TO BANK m1,2,3,4,5,6
CURRENT STATE CS\ RAS\ CAS\ WE\ COMMAND (ACTION) H X X X COMMAND INHIBIT (NOP/Continue previous operation) Any L H H H NO OPERATION (NOP/Continue previous operation) Idle X X X X Any Command Otherwise Allowed to Bank m L L H H ACTIVE (Select and active row) Row Activating, L H L H READ (Select column and start READ burst) Active, or L H L L WRITE (Select column and start WRITE burst) Precharging L L H L PRECHARGE L L H H ACTIVE (Select and active row) Read L H L H READ (Select column and start new READ burst) (Auto Precharge L H L L WRITE (Select column and start WRITE burst) Disabled) L L H L PRECHARGE L L H H ACTIVE (Select and active row) Write L H L H READ (Select column and start READ burst) (Auto Precharge L H L L WRITE (Select column and start new WRITE burst) Disabled) L L H L PRECHARGE L L H H ACTIVE (Select and active row) Read L H L H READ (Select column and start new READ burst) (with Auto L H L L WRITE (Select column and start WRITE burst) Precharge) L L H L PRECHARGE L L H H ACTIVE (Select and active row) Write L H L H READ (Select column and start READ burst) (with Auto L H L L WRITE (Select column and start new WRITE burst) Precharge) L L H L PRECHARGE
7 7
7, 10 7, 11 9 7, 12 7, 13 9 7, 8, 14 7, 8, 15 9 7, 8, 16 7, 8, 17 9
NOTES:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Read w/ Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/ Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. (continued on next page) 6. All states and sequences not shown are illegal or reserved.
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NOTES (continued):
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m listed in the Command column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. CONCURRENT AUTO PRECHARGE: bank n will initiate the auto precharge command when its burst has been interrupted by bank m's burst. 9. Burst in bank n continues as initiated. 10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later (Figure 7). 11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the WRITE command to prevent bus contention. 12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ on bank m. 13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 25). 15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25). 16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 26). 17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Figure 27).
AS4SD2M32
AS4SD2M32 Rev. 1.0 1/08
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SDRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD, VDDQ Supply Relative to VSS...................................................-1V to +4.6V Voltage on Inputs, NC or I/O Pins Relative to VSS...................................................-1V to +4.6V Operating Temperature, TA (IT)..................................-40C to +85C Operating Temperature, TA (ET)..............................-45C to +105C Operating Temperature, TA (XT)..............................-55C to +125C Storage Temperature (plastic)..................................-55C to +150C Power Dissipation...........................................................................1W
AS4SD2M32
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity (plastics).
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS1,5,6 (VDD, VDDQ = +3.3V 0.3V)
PARAMETER Supply Voltage Input High Voltage: Logic 1; All inputs Input Low Voltage: Logic 0; All inputs Input Leakage Current: Any input 0V < VIN < VDD (All other pins not under test = 0V) Output Leakage Current: DQs are disabled: 0V < VOUT < VDDQ Output Levels: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) SYMBOL VDD, VDDQ VIH VIL II IOZ VOH VOL MIN 3 2.2 -0.3 -5 -5 2.4 --MAX 3.6 VDD+ 0.3 0.8 5 5 --0.4 UNITS V V V A A V V 22 22 NOTES
IDD SPECIFICATIONS AND CONDITIONS1,5,6,11,13 (VDD, VDDQ = +3.3V 0.3V)
PARAMETER Operating Current: Active Mode; Burst = 2; READ or WRITE; t RC = tRC (MIN) Standby Current: Power-Down Mode; All banks idle; CKE = LOW Standby Current: Active Mode; CKE = HIGH; CS\ = HIGH; All banks active after tRCD met; No accesses in progress Operating Current: Burst Mode; Continuous Burst; READ or WRITE: All banks active Auto Refresh Current CS\ = HIGH; CKE = HIGH SELF REFRESH CURRENT: CKE < 0.2V
AS4SD2M32 Rev. 1.0 1/08
SYMBOL MAX (-6) IDD1 IDD2 150 8
UNITS mA mA
NOTES 3, 18, 19, 32 32 3, 12, 19, 32 3, 18, 19, 32 3, 12, 18, 19, 32, 33 4, 35
IDD3
8
mA
IDD4 IDD5 IDD6 IDD7
185 300 6 1
mA mA mA mA
tRFC = tRFC (MIN) tRFC = 7.81 s
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SDRAM
Austin Semiconductor, Inc.
CAPACITANCE2
PARAMETER Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQs SYM CI1 CI2 CIO MIN 2 2 4.0 MAX 4 4 5.0 UNITS pF pF pF NOTES 29 30 31
AS4SD2M32
AC FUNCTIONAL CHARACTERISTICS5,6,7,8,9,11
PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data high-impedance during READs WRITE command to input data delay Data-in to ACTIVE command Data-in to PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command CL = 3 CL = 2 SYMBOL -6, -7, -75 tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDPL tBDL tCDL tRDL tMRD tROH(3) tROH(2) 1 1 1 0 0 2 0 5 2 1 1 2 2 3 2 UNITS tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK NOTES 17 14 14 17 17 17 17 15, 21 16, 21 17 17 16, 21 26 17 17
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SDRAM
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AS4SD2M32
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS5,6,8,9,11
-6 PARAMETER Access time from CLK (pos. edge) Address hold time Address setup time CLK high-level width CLK low-level width Clock cycle time CKE hold time CKE setup time CS\, RAS\, CAS\, WE\, DQM hold time CS\, RAS\, CAS\, WE\, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time (load) Data-out hold time (no load) ACTIVE to PRECHARGE command ACTIVE to ACTIVE command ACTIVE to READ or WRITE delay Refresh period (4,092 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time Exit SELF REFRESH to ACTIVE command CL = 3 CL = 2 CL = 3 CL = 2 CL = 3 CL = 2 SYM tAC(3) tAC(2) tAH tAS tCH tCL tCK(3) tCK(2) tCKH tCKS tCMH tCMS tDH tDS tHZ(3) tHZ(2) tLZ tOH tOHN tRAS tRC tRCD tREF tRFC tRP tRRD tT tWR tXSR 60 18 12 0.3 1 CLK + 6ns 70 1.2 0 2 1.3 37.5 60 18 64/16 70 20 14 0.3 1 CLK + 7ns 70 1.2 120K 0.8 1.5 2 2 6 10 0.8 1 0.8 1.5 0.8 1.5 5.5 7.5 0 2.5 1.5 37.5 63 20 64/16 70 20 15 0.3 1 CLK + 7.5ns 15 75 1.2 120K MIN MAX 5.5 7.5 8 0.8 1.5 2.5 2.5 7 10 0.8 1 0.8 1.5 0.8 1.5 5.5 8 0 3 1.8 37.5 70 20 64 / 16 120K MIN -7 MAX 5.5 8 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 0.8 1.5 0.8 1.5 5.5 8 MIN -75 MAX 5.4 8 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns 7 24 25 20, 35 34 35 28 10 10 23 23 NOTES 27
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
29
SDRAM
Austin Semiconductor, Inc.
NOTES:
1. All voltages referenced to VSS. 2. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25C; pin under test biased at 1.4V. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured: (0C < TA < +125C for XT), (-40C < TA < +85C for IT), and (-45C < TA < +105C for ET). 6. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at the same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured at 1.5V with equivalent load:
AS4SD2M32
Q 50pF
10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC operating and IDD test conditions have VIL = 0V and VIH = 3.0V using a measurement reference level of 1.5V. If the input transition time is longer than 1ns, then the timing is measured from VIL (MAX) and VIH (MIN) and no longer from the 1.5V mid-point. 12. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.
AS4SD2M32 Rev. 1.0 1/08
18. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 7.5ns for -75. 22. VIH overshoot: VIL (MAX) = VDDQ = 2V for a pulse width < 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width < 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns after the first clock delay, after the last WRITE is executed. May not exceed limit set for precharge mode. 25. Precharge mode only. 26. JEDEC and PC100 specify three clock. 27. for -75 at CL = 3 with no load is 4.6ns and is guaranteed by design. 28. Parameter guaranteed by design. 29. PC100 specifies a maximum of 4pF. 30. PC100 specifies a maximum of 5pF. 31. PC100 specifies a maximum of 6.5pF. 32. CL = 3 and tCK = 7.5ns. 33. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value. 34. 64ms refresh for IT, ET temperature options, 16ms refresh for XT temperature option. 35. Self refresh mode available for IT and ET only.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
30
SDRAM
Austin Semiconductor, Inc.
AS4SD2M32
INITIALIZE AND LOAD MODE REGISTER2
DQMx
A0-A9
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
31
SDRAM
Austin Semiconductor, Inc. POWER DOWN MODE1
AS4SD2M32
DQMx
A0-A9
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
32
SDRAM
Austin Semiconductor, Inc. CLOCK SUSPEND MODE1
AS4SD2M32
DQMx A0-A9
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
33
SDRAM
Austin Semiconductor, Inc.
AS4SD2M32
AUTO REFRESH MODE (IT & ET Temp options ONLY)
DQMx
A0-A9
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
34
SDRAM
Austin Semiconductor, Inc.
AS4SD2M32
SELF REFRESH MODE (IT & ET Temp options ONLY)
DQMx
A0-A9
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
35
SDRAM
Austin Semiconductor, Inc. READ - WITHOUT AUTO PRECHARGE1
AS4SD2M32
DQMx
A0-A9
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
36
SDRAM
Austin Semiconductor, Inc. READ - WITH AUTO PRECHARGE1
AS4SD2M32
DQMx
A0-A9
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
37
SDRAM
Austin Semiconductor, Inc.
AS4SD2M32
SINGLE READ - WITHOUT AUTO PRECHARGE1
DQMx A0-A9
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
38
SDRAM
Austin Semiconductor, Inc.
AS4SD2M32
SINGLE READ - WITH AUTO PRECHARGE1
DQMx A0-A9
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
39
SDRAM
Austin Semiconductor, Inc.
AS4SD2M32
ALTERNATING BANK READ ACCESSES1
DQMx
A0-A9
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
40
SDRAM
Austin Semiconductor, Inc. READ - FULL-PAGE BURST1
AS4SD2M32
DQMx
A0-A9
1,024 (x16) locations within same row
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
41
SDRAM
Austin Semiconductor, Inc. READ - DQM OPERATION1
AS4SD2M32
DQMx
A0-A9
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
42
SDRAM
Austin Semiconductor, Inc. WRITE - WITHOUT AUTO PRECHARGE1
AS4SD2M32
DQMx
A0-A9
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
43
SDRAM
Austin Semiconductor, Inc. WRITE - WITH AUTO PRECHARGE1
AS4SD2M32
DQMx
A0-A9
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
44
SDRAM
Austin Semiconductor, Inc.
AS4SD2M32
SINGLE WRITE - WITHOUT AUTO PRECHARGE1
DQMx
A0-A9
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
45
SDRAM
Austin Semiconductor, Inc.
AS4SD2M32
SINGLE WRITE - WITH AUTO PRECHARGE1
DQMx
A0-A9
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
46
SDRAM
Austin Semiconductor, Inc.
AS4SD2M32
ALTERNATING BANK WRITE ACCESSES1
DQMx
A0-A9
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
47
SDRAM
Austin Semiconductor, Inc. WRITE - FULL-PAGE BURST
AS4SD2M32
DQMx
A0-A9
1,024 (x16) locations within same row
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
48
SDRAM
Austin Semiconductor, Inc. WRITE - DQM OPERATION1
AS4SD2M32
DQMx
A0-A9
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
49
SDRAM
Austin Semiconductor, Inc. MECHANICAL DEFINITIONS (Package Designator DGX)
AS4SD2M32
N
N/2+1
E1
E
Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be
measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
1 D
N/2
SEATING PLANE
ZD
A
e
b
L A1
C
Symbol Ref. Std. No. Leads (N) A A1 A2 b C D E1 E e L L1 ZD
Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 54 -- 0.047 0.002 0.006 -- -- 0.012 0.018 0.005 0.0083 0.867 0.8827 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 -- -- 0 8
Plastic TSOP (T - Type II) Millimeters Inches Symbol Min Max Min Max Ref. Std. No. Leads (N) 86 A A1 A2 b C D E1 E e L L1 ZD -- 1.20 0.05 0.15 0.95 1.05 0.17 0.27 0.12 0.21 22.02 22.42 10.16 BSC 11.56 11.96 0.50 BSC 0.40 0.60 0.80 REF 0.61 REF 0 8 -- 0.047 0.002 0.006 0.037 0.041 0.007 0.011 0.005 0.008 0.867 0.8827 0.400 BSC 0.455 0.471 0.020 BSC 0.016 0.024 0.031 REF 0.024 BSC 0 8
-- 1.20 0.05 0.15 -- -- 0.30 0.45 0.12 0.21 22.02 22.42 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 -- -- 0.71 REF 0 8
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
50
SDRAM
Austin Semiconductor, Inc.
AS4SD2M32
ORDERING INFORMATION
Device Number AS4SD2M32DGX-6IT AS4SD2M32DGX-7IT AS4SD2M32DGX-75IT AS4SD2M32DGX-6ET AS4SD2M32DGX-7ET AS4SD2M32DGX-75ET AS4SD2M32DGX-6XT AS4SD2M32DGX-7XT AS4SD2M32DGX-75XT Speed Grade Package Screening Industrial Industrial Industrial Enhanced Enhanced Enhanced Extended Extended Extended
166MHz TSOPII-86LD 143MHz TSOPII-86LD 133MHz TSOPII-86LD 166MHz TSOPII-86LD 143MHz TSOPII-86LD 133MHz TSOPII-86LD 166MHz TSOPII-86LD 143MHz TSOPII-86LD 133MHz TSOPII-86LD
*AVAILABLE PROCESSES IT = Industrial Temperature Range ET = Enhanced Temperature Range XT = Extended (Military) Temperature Range
-40oC to +85oC -45C to +105C -55oC to +125oC
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
51
SDRAM
Austin Semiconductor, Inc.
DOCUMENT TITLE 512K x 32 x 4 Banks (64-Mb) Synchronous SDRAM REVISION HISTORY Rev # 1.0 History Initial Release Release Date January 2008 Status Preliminary
AS4SD2M32
AS4SD2M32 Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
52

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